Certain embodiments of the present invention relate to the synthesis of a clock signal. More specifically, certain embodiments relate to a method and apparatus for efficiently synthesizing a clock signal on a chip such that the synthesized clock signal has a 50% duty cycle. The synthesized clock signal is derived from a system clock signal that is at half the frequency of the synthesized clock signal and whose duty cycle is not required to be 50%.
Highly integrated System-on-Chip (SOC) implementations require clock synthesis and generation to be available on-chip. High speed and high-density memory designs require precise clocking elements to meet timing requirements. For example, one application is to double clock an embedded memory to make the embedded memory appear as a dual port. Double clocking may be accomplished, in part, by doubling the frequency of an existing system clock signal.
Many embedded on-chip clock synthesis implementations consume significant amounts of power and chip area and also are dependent on the duty cycle of a system clock signal from which the synthesized clock signal is being derived. It is often desirable for a synthesized clock signal to have a 50% duty cycle, being independent of the clock signal from which the synthesized clock signal is derived. It is also desirable to synthesize a clock signal in an efficient manner to minimize power consumed and chip area consumed by the clock synthesizing circuitry.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings.
An embodiment of the present invention provides an efficient approach to synthesize a new clock signal from a current clock signal such that the new clock signal is at twice the frequency of the current clock signal. The new clock signal has a duty cycle of 50% that is not dependent on the duty cycle of the current clock signal.
An efficient method is provided for doubling a first frequency of a first clock signal. The method includes generating a second clock signal at a second frequency by dividing the first frequency of the first clock signal by two, such that the second frequency is half of the first frequency and a duty cycle of the second clock signal is 50%. The method also includes generating a set of phase-delayed clock signals in response to the second clock signal such that the set of phase-delayed clock signals are delayed in phase with respect to the second clock signal. The method further includes combining the set of phase-delayed clock signals to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of the third clock signal is 50%.
Apparatus is provided for doubling a first frequency of a first clock signal. The apparatus includes a divide-by-two circuit that generates a second clock signal at a second frequency that is half of the first frequency, such that a duty cycle of the second clock signal is 50%. The apparatus also includes a delay locked loop (DLL) circuit responsive to the second clock signal to generate a set of phase-delayed clock signals that are delayed in phase with respect to the second clock signal. Further, the apparatus includes a phase combiner circuit responsive to the set of phase-delayed clock signals to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of said third clock signal is 50%.
Certain embodiments of the present invention afford an efficient approach for synthesizing a new clock signal from a current clock signal by doubling the frequency of the current clock signal and establishing a 50% duty cycle for the new clock signal that is not dependent on the duty cycle of the current clock signal.